1. Field of the Invention
The present invention relates to a method for enhancing reliability of information transmission in TDMA wireless communication system, and more particularly, in a low-rate TDMA system.
2. Description of the Prior Art
In TDMA-based digital wireless communication system, carriers are transmitted in time slots of various length (for example 30 ms). One burst structure is transmitted within a time slot, and there are certain guard intervals between different time slots.
Data are transmitted within frame time slots by TDMA transmitters. At the beginning of transmission, transmission power of carriers on time slots will be increased continually and then be kept at a steady state, and at the end of the transmission the transmission power will be decreased continually and then be kept a steady state. This process keeps repeating during communicating with the transmitter.
For the voltage controlled oscillator (VCO), there needs time period to control the process of the power increasing and decreasing within frame time slots, during which the signals are not stable. It is very easy to interfere these instable signals to cause errors in decoding. Meanwhile, adjacent channel interference may be resulted therefrom, and thus the normal operation of other systems may be affected. In particular, with regard to TDMA system which requires fast-speed power switch, such phenomenon, as well as effects on the whole system becomes even more obvious.
With regard to TDMA wireless communication system, distribution of power increasing and decreasing during the frame time slot is shown as FIG. 1, and here, given that its time slot is 30 ms.
FIG. 1 illustrates the relationship of power with time in a time slot in a TDMA wireless communication system. The time slot of 30 ms is divided into 3 regions. Region A represents a power increase stage, which duration is related with VCO performance. The increase time may be less than or equal to 1.5 ms according to the current VCO accuracy. Region B represents a power-steady stage, which duration depends on the length of the time slot (27.5 ms as defined here). Region C represents a power decrease stage, with its duration around 1.5 ms. Generally, it is necessary to make the falling curve smooth for achieving a lower adjacent channel power, thus the power must be decreased at the rear end of Region B.
However, as for Region B, the performance of signals in the part may be affected by power decreasing in advance; and likely, the performance of signals at the front end may be impacted by the power fluctuation for smoothing increase curve. That is to say, owing to the inherent property of VCO power adjustment, the quality of signals at both ends of Region B will be degraded. And thus, probability of signal errors and bit error rate are higher than ever.
Therefore, specific measures should be taken to perform ECC protection on signals in both ends.
In the prior art, methods for protecting the signals at the both ends of Region B from degrading comprising the following step of:
Encoding data to be grouped in a frame at first by using BPTC. BPTC, namely short of Block Product Turbo Codes, is applied widely to error correcting coding on the link layer channel in wireless communication system. BPTC is a simple algorithm, in which the code words are arranged into a matrix, so as to provide a certain ECC (for example Hamming code) protection for rows and columns separately.
Taking it for example, supposing that the valid information bits to be transmitted are 96 bits, at first we need to encode the data by using BPTC (96, 196), which indicates that the information bits are 96 bits and the code words after encoded are 196 bits. The data are encoded in this way: add three zeros to the front of information bits for forming 99 bits; arrange the 99 bits in a 9×11 matrix; perform left-to-right error correction per row by Hamming codes (15, 11, 3) to get a 9×15 matrix; and go on with top-to-bottom error-correction per column by Hamming codes (13, 9, 3) to get a 11×15 matrix as shown in FIG. 2.
In FIG. 2, I (0)-I (95) are information bits, and H_R is the Error Correcting Code of Hamming codes (15, 11, 3), and H_C is the Error Correcting Code of Hamming codes (11, 9, 3).
As for the BPTC encode matrix formed in Step 1 of FIG. 2, it is needed to disarrange the bits by applying a certain interleaving method and then rearrange and transmit them in a certain sequence. Interleaving is applied to decentralize burst errors occurred during information transmission. Therefore, this method may help achieve reasonable re-allocation of error information occurred during power increase and power decrease on time slots per TDMA frame.
With reference to the prior art, the BPTC encode matrix (see FIG. 2) formed in Step 1 is interleaved and transmitted in the following order:
Firstly, rearrange rows of the matrix in FIG. 2 from left to right, and then the columns from top to bottom. Accordingly, decompose the 11×15 matrix into a 1×195 row vector. And FIG. 3 illustrates the decomposition and construction steps:
as for the 1×195 vector, the left side is the least significant bit, and the right the most. Suppose that the number of the index ranges 0 ˜194, with each corresponding to R2˜H_C15(0), and the following interleaving formulas are adopted:Interleave Index=Index×13 modulo 196  (1)
Accordingly, the bit sequence is disarranged after such interleaving process. Check bits and information bits become mixed, and constitute a new transmission sequence, wherein the Error Correcting Code of Hamming code is most probably arranged at both ends of a frame time slot, thus enhancing the anti-interference capability of data in this part.
Certainly, there is not only the above interleaving formula. The interleaving formulas or the bit sequence may be modified to arrange the redundancy bits of the Error Correcting Code at both ends of the time slot in a frame for a better effect. For example, better effect can be attained by using the following formula:Interleave Index=Index×181 modulo 196  (2)
The final transmission sequence depends on the sequence of interleaved bits, i.e. the Interleave Index in Formulas 1 and 2. In the table accompanying the specification, the bit name, sequences before interleaving and after interleaving, and a corresponding relationship between these items are listed. Therefore, the bits will be transmitted according to the interleaved index.
In the prior art, the reliability of data at both ends of the frame time slots may be enhanced, and the bit-error rate may be decreased through encoding the valid information bits by using BPTC, providing error control using Hamming code for rows and columns, and arranging the ECC check bits as much as possible into the both ends on the frame time slots by using a certain convolution method.
Through such a technique data at both ends of frame time slots may be protected and the bit-error rate may be decreased. However, there are many defects to be improved:
(1) Incapable to enhance error correcting capability at the both ends of the frame time slots, as the example above, error correcting capability at both ends of frame time slots corresponds to that of Hamming code, which is not enhanced in fact;
(2) Incapable to arrange all redundancy bits at the both ends of the frame time slots through various interleaving methods. Here, some valid information bits will be still allocated into the both ends, which may increase the risk of error bit from valid information.